Changeset 883


Ignore:
Timestamp:
Jun 6, 2012 2:34:08 PM (10 years ago)
Author:
mooney
Message:

initial edits

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1 edited

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  • softGlue_examples/source/gated_scaler/index.rst

    r882 r883  
    1515
    1616This circuit implements four counter channels, a time base to control counting
    17 time, an overall gate, and additional circuitry to control starting,
    18 stopping, and processing of the count-value records.
     17time, an overall gate, and additional circuitry to control starting,  stopping,
     18and processing of the count-value records.  Note that the :index:`interrupt
     19<interrupt; in gated scaler>` configuration for I/O bit 17, and the sseq record
     20that causes counter values to be read, are not shown.
    1921
    2022Requirements
    2123------------
    2224
    23 This circuit uses a busy record (from the busy module) and a sseq record (from
     25This circuit uses a :index:`busy record <busy record; in gated scaler>` (from
     26the busy module) and a :index:`sseq record <sseq record; in gated scaler>` (from
    2427the std module, but moved to the calc module for synApps 5.7), which are loaded
    25 by softGlue_convenience.db.  If these records are not available, the circuit
     28by ``softGlue_convenience.db``.  If these records are not available, the circuit
    2629will still function, but the counters will not be read immediately after the
    2730count time has elapsed, and it will not be useful to drive the counter with a
    28 ca_put_callback(), because the callback will come immediately, instead of coming
    29 after counting has finished.
     31``ca_put_callback()``, because the callback will come immediately, instead of
     32coming after counting has finished.
    3033
    3134Usage
     
    3437To load the circuit into softGlue:
    3538
    36 1) Download this BURT snapshot file :download:`gatedScaler.snap <gatedScaler.snap>`
    37        
    38 2) Edit the file to replace all occurrences of the string "xxx:softGlue:"
    39    with whatever value you specified for $(P)$(H) when you loaded softGlue into
    40    your IOC
     391) Download this `BURT <http://www.aps.anl.gov/epics/extensions/burt/index.php>`_ snapshot file :download:`gatedScaler.snap
     40<gatedScaler.snap>`
    4141
     422) Edit the file to replace all occurrences of the string ``xxx:softGlue:`` with
     43   whatever value you specified for ``$(P)$(H)`` when you loaded softGlue into
     44   your IOC.
    4245
    43 3) Load the file with the command "burtwb -f gatedScaler.snap"
     463) Load the file with the command ``burtwb -f gatedScaler.snap``
    4447
    4548To use the circuit:
     
    47501)      Connect field inputs to the counters by giving names to four field input
    4851        bits, and writing those names also to the clock inputs for up counters 1-4.
    49         (As delivered, all counters count the signal named "Clock_8MHz", which is
     52        (As delivered, all counters count the signal named ``Clock_8MHz``, which is
    5053        the name this circuit gives to the 8 MHz clock.)
    5154
    52 2)      Set the count time by writing a number, to the "N" input of DivByN-1.  The
    53         timebase clock is 8 MHz, so the actual count time will be N/8e6 seconds.
     552)      Set the count time by writing a number, to the ``N`` input of ``DivByN-1``.
     56        The timebase clock is 8 MHz, so the actual count time will be N/8
     57        microseconds.
    5458
    55 3)      Start the counter by writing 1 to $(P)$(H)busy1 (one of the busy records
    56         in the EPICS database, softGlue_convenience.db, which is loaded by the
    57         standard softGlue.cmd file).
     593)      Start the counter by writing ``1`` to ``$(P)$(H)busy1`` (one of the busy
     60        records in the EPICS database ``softGlue_convenience.db``, which is loaded by
     61        the standard ``softGlue.cmd`` file).
    5862
    59634)      Either wait for the count time to elapse, or abort the count by writing
    60         0 to $(P)$(H)busy1.
     64        ``0`` to ``$(P)$(H)busy1``.
    6165
    62 5)      Read the accumulated counts from UpCntr-<n>_COUNTS, where <n> is in [1-4].
     665)      Read the accumulated counts from ``UpCntr-<n>_COUNTS``, where ``<n>`` is in
     67        [1-4].
    6368
    64696)      Gating can be done either by EPICS, or by a field input.
    6570
    66         To gate with EPICS, write '1' to the second input of AND-1 to enable
    67         counting, or '0' to disable counting.
     71        To gate with EPICS, write ``1`` to the second input of ``AND-1`` to enable
     72        counting, or ``0`` to disable counting.
    6873
    6974        To gate from a field input, give the field input a signal name, and write
    70         that same name to the second input of AND-1.
     75        that same name to the second input of ``AND-1``.
    7176
    7277        The time-base counter also is gated, though you can have only the counter
    73         channels gated by changing the "EN" input of DivByN-1 from "gatedStart" to
    74         "start".
     78        channels gated by changing the ``EN`` input of ``DivByN-1`` from
     79        ``gatedStart`` to ``start``.
    7580
    7681Theory of operation
    7782-------------------
    7883
    79 Execution begins when the user writes 1 to $(P)$(H)busy1.  This record declares
    80 itself to be busy (for the purpose of ca_put_callback()), and starts the counter
    81 circuit by writing the value 1 to the input of BUF-1.  BUF-1 fans the signal
    82 out, as the signal named "count", to the clock inputs of flip flops DFF2 and
    83 DFF-4.  "count" will stay at 1 until the counters are finished counting.
     84Execution begins when the user writes ``1`` to ``$(P)$(H)busy1``.  This record declares
     85itself to be busy (for the purpose of ``ca_put_callback()``), and starts the counter
     86circuit by writing the value ``1`` to the input of ``BUF-1``.  ``BUF-1`` fans the signal
     87out, as the signal named ``count``, to the clock inputs of flip flops ``DFF-2`` and
     88``DFF-4``.  ``count`` will stay at ``1`` until the counters are finished counting.
    8489
    85 *       DFF-4 makes an extremely short pulse (named "clear") from the rising edge of
    86         "count".
     90*       ``DFF-4`` makes an extremely short pulse (named ``clear``) from the rising edge of
     91        ``count``.
    8792
    88 *       DFF-2 makes an extremely short pulse (named "abort") from the falling edge
    89         of "count".
     93*       ``DFF-2`` makes an extremely short pulse (named ``abort``) from the falling edge
     94        of ``count``.
    9095
    91 "clear" zeroes the counters (UpCntr-<n>), and loads the count time (i.e., the
    92 number of clock pulses) into the time base DivByN-1.  "clear*" sets the output
    93 of DFF-3 to 1, producing the signal "counting", which stays at 1 until it's time
    94 for the counters to stop counting.
     96``clear`` zeroes the counters (``UpCntr-<n>``), and loads the count time (i.e.,
     97the number of clock pulses) into the time base ``DivByN-1``.  ``clear*`` sets
     98the output of ``DFF-3`` to ``1``, producing the signal ``counting``, which stays
     99at ``1`` until it's time for the counters to stop counting.
    95100
    96 "counting" is sent to field output bit 17, which must actually be configured as
     101``counting`` is sent to field output bit 17, which must actually be configured as
    97102an output, and which will generate an interrupt on the falling edge of
    98 "counting" (when pulse counting has finished).  The interrupt configuration
    99 (which is not shown in the figure) is set so that the falling edge of "counting"
    100 causes the record $(P)$(H)sseq1 to process, which causes EPICS records for all
     103``counting`` (when pulse counting has finished).  The interrupt configuration
     104(which is not shown in the figure) is set so that the falling edge of ``counting``
     105causes the record ``$(P)$(H)sseq1`` to process, which causes EPICS records for all
    101106four counters to process, reading their values so that a client can acquire
    102107them.
     
    109114       
    110115*       The counter doesn't actually rely on the interrupt.  It's only needed to get
    111         the counter values read from hardware promptly.  The counters will
    112         eventually be read in any case, by the periodic update $(P)$(H)ReadRate.
    113         But a fast client (such as the sscan record) will not want to wait for this
    114         periodic read, nor will it know when the read has occurred.
     116        the counter values read from hardware promptly - before the busy record is
     117        cleared, indicating that counting is done.  The counters will eventually be
     118        read in any case, by the periodic update ``$(P)$(H)ReadRate``.  But a fast
     119        client (such as the sscan record) will not want to wait for this periodic
     120        read, nor will it know when the read has occurred.
    115121
    116 "counting" is sent to AND-1 to be ANDed with the user's gate signal (the second
    117 input of AND-1), producing the signal "gatedCounting".  As delivered, the gate
    118 signal is simply 1.  The user can gate counting off by writing 0 to the gate
    119 signal, or the user can implement a hardware gate as described above in "Usage".
     122``counting`` is sent to ``AND-1`` to be ANDed with the user's gate signal (the
     123second input of ``AND-1``), producing the signal ``gatedCounting``.  As
     124delivered, the gate signal is simply ``1``.  The user can gate counting off by
     125writing ``0`` to the gate signal, or the user can implement a hardware gate as
     126described above in "Usage".
    120127
    121 "gatedCounting" enables the counters and the time base, DivByN-1.  When the
    122 specified number of clock pulses have been received by DivByN-1, its output,
    123 "stopTime", goes to 1 for one clock pulse.
     128``gatedCounting`` enables the counters and the time base, ``DivByN-1``.  When the
     129specified number of clock pulses have been received by ``DivByN-1``, its output,
     130``stopTime``, goes to ``1`` for one clock pulse.
    124131
    125 "stopTime" is delivered to OR-1, to be ORed with the "abort" signal mentioned
    126 earlier.  When either "stopTime" or "abort" goes to 1, DFF-3 is cleared,
    127 rescinding "counting", which causes all counters and the time base to cease
     132``stopTime`` is delivered to ``OR-1``, to be ORed with the ``abort`` signal mentioned
     133earlier.  When either ``stopTime`` or ``abort`` goes to ``1``, ``DFF-3`` is cleared,
     134rescinding ``counting``, which causes all counters and the time base to cease
    128135counting.
    129136
    130 When "counting' goes to 0, an interrupt is generated.  The interrupt causes the
    131 string-sequence record to process the counter-value records
    132 ($(P)$(H)UpCntr-<n>_COUNTS, where <n> is in [1-4]) so their values will be
     137When ``counting`` goes to ``0``, an interrupt is generated.  The interrupt
     138causes the sseq record to process the counter-value records
     139(``$(P)$(H)UpCntr-<n>_COUNTS``, where ``<n>`` is in [1-4]) so their values will be
    133140available to be read by an EPICS client.  The string-sequence record also sets
    134 $(P)$(H)busy1 to 0, signalling completion to EPICS.
     141``$(P)$(H)busy1`` to ``0``, signalling completion to EPICS.
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