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1.. $Id: index.rst 955 2012-06-20 20:13:11Z mooney $
4Gated scaler
8This circuit shows one way to build a four channel :index:`!gated scaler`.
10Circuit and documentation: Tim Mooney
15.. image:: gatedScaler.gif
16        :width: 100%
18This circuit implements four counter channels, a time base to control counting
19time, an overall gate, and additional circuitry to control starting,  stopping,
20and processing of the count-value records.  Note that the :index:`interrupt
21<interrupt; in gated scaler>` configuration for I/O bit 17, and the sseq record
22that causes counter values to be read, are not shown.
27This circuit uses a :index:`busy record <busy record; in gated scaler>` (from
28the `synApps <>`_ busy module) and a :index:`sseq record <sseq record; in gated scaler>` (from
29the synApps std module, but moved to the calc module for synApps 5.7), which are loaded
30by ``softGlue_convenience.db``.  If these records are not available, the circuit
31will still function, but the counters will not be read immediately after the
32count time has elapsed, and it will not be useful to drive the counter with a
33``ca_put_callback()``, because the callback will come immediately, instead of
34coming after counting has finished.
39To load the circuit into softGlue:
411) Download this `BURT <>`_ snapshot file :download:`gatedScaler.snap
442) Edit the file to replace all occurrences of the string ``xxx:softGlue:`` with
45   whatever value you specified for ``$(P)$(H)`` when you loaded softGlue into
46   your IOC.
483) Load the file with the command ``burtwb -f gatedScaler.snap``
50To use the circuit:
521)      Connect field inputs to the counters by giving names to four field input
53        bits, and writing those names also to the clock inputs for up counters 1-4.
54        (As delivered, all counters count the signal named ``Clock_8MHz``, which is
55        the name this circuit gives to the 8 MHz clock.)
572)      Set the count time by writing a number, to the ``N`` input of ``DivByN-1``.
58        The timebase clock is 8 MHz, so the actual count time will be N/8
59        microseconds.
613)      Start the counter by writing ``1`` to ``$(P)$(H)busy1`` (one of the busy
62        records in the EPICS database ``softGlue_convenience.db``, which is loaded by
63        the standard ``softGlue.cmd`` file).
654)      Either wait for the count time to elapse, or abort the count by writing
66        ``0`` to ``$(P)$(H)busy1``.
68        .. note::       A better way to abort would be to write ``0`` to the input of
69                                ``BUF-1``. This is better because it results in the counters
70                                being read before the busy record is cleared.
725)      Read the accumulated counts from ``UpCntr-<n>_COUNTS``, where ``<n>`` is in
73        [1-4].
756)      Gating can be done either by EPICS, or by a field input.
77        To gate with EPICS, write ``1`` to the second input of ``AND-1`` to enable
78        counting, or ``0`` to disable counting.
80        To gate from a field input, give the field input a signal name, and write
81        that same name to the second input of ``AND-1``.
83        The time-base counter also is gated, though you can have only the counter
84        channels gated by changing the ``EN`` input of ``DivByN-1`` from
85        ``gatedStart`` to ``start``.
87Theory of operation
90Execution begins when a client writes ``1`` to ``$(P)$(H)busy1``.  This record declares
91itself to be busy (for the purpose of ``ca_put_callback()``), and starts the counter
92circuit by writing the value ``1`` to the input of ``BUF-1````BUF-1`` fans the signal
93out, as the signal named ``count``, to the clock inputs of flip flops ``DFF-2`` and
94``DFF-4````count`` will stay at ``1`` until the counters are finished counting.
96*       ``DFF-4`` makes an extremely short pulse (named ``clear``) from the rising edge of
97        ``count``.
99*       ``DFF-2`` makes an extremely short pulse (named ``abort``) from the falling edge
100        of ``count``.
102``clear`` zeroes the counters (``UpCntr-<n>``), and loads the count time (i.e.,
103the number of clock pulses) into the time base ``DivByN-1````clear*`` sets
104the output of ``DFF-3`` to ``1``, producing the signal ``counting``, which stays
105at ``1`` until it's time for the counters to stop counting.
107``counting`` is sent to field output bit 17, which must actually be configured
108as an output, and which will generate an interrupt on the falling edge of
109``counting`` (when pulse counting has finished).  The interrupt configuration
110(which is not shown in the figure) is set so that the falling edge of
111``counting`` causes the record ``$(P)$(H)sseq1`` to process, which causes EPICS
112records for all four counters to process, reading their values so that a client
113can acquire them, and then clears the busy record ``$(P)$(H)busy1``.  If the
114client that started the scaler did so with a ``ca_put_callback()``, clearing the
115busy record results in a "done" callback to that client.
117*       You can, of course, use any field output bit for this purpose, as long as
118        you configure it correctly.
120*       The only reason for using an output bit is to generate an interrupt when the
121        counting is finished.
123*       The counter doesn't actually rely on the interrupt.  It's only needed to get
124        the counter values read from hardware promptly - before the busy record is
125        cleared, indicating that counting is done.  The counters will eventually be
126        read in any case, by the periodic update ``$(P)$(H)ReadRate``.  But a fast
127        client (such as the sscan record) will not want to wait for this periodic
128        read, nor will it know when the read has occurred.
130``counting`` is sent to ``AND-1`` to be ANDed with the user's gate signal (the
131second input of ``AND-1``), producing the signal ``gatedCounting``.  As
132delivered, the gate signal is simply ``1``.  The user can gate counting off by
133writing ``0`` to the gate signal, or the user can implement a hardware gate as
134described above in "Usage".
136``gatedCounting`` enables the counters and the time base, ``DivByN-1``.  When the
137specified number of clock pulses have been received by ``DivByN-1``, its output,
138``stopTime``, goes to ``1`` for one clock pulse.
140``stopTime`` is delivered to ``OR-1``, to be ORed with the ``abort`` signal mentioned
141earlier.  When either ``stopTime`` or ``abort`` goes to ``1``, ``DFF-3`` is cleared,
142rescinding ``counting``, which causes all counters and the time base to cease
145When ``counting`` goes to ``0``, an interrupt is generated.  The interrupt
146causes the sseq record to process the counter-value records
147(``$(P)$(H)UpCntr-<n>_COUNTS``, where ``<n>`` is in [1-4]) so their values will be
148available to be read by an EPICS client.  The string-sequence record also sets
149``$(P)$(H)busy1`` to ``0``, signalling completion to EPICS.
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